寄存器描述

此域用于表示 Debug Port Number。

Port Indicators

This bit indicates whether the ports support port indicatorcontrol. When this bit is a one, the port status and controlregisters include a read/writeable field for controllingthe state of the port indicator.

Number of Companion Controller，表示此 USB 2.0 Host Controller 包括了多少个 Companion Controller，这里只有一个 OHCI HostControlller。

Number of ports supported per companion host controller，表示每个 Companion Controller 支持的端口数，这里只有一个端口。

• 0x0：The first N_PCC ports are routed to the lowest numbered function companion host controller, the next N_PCC port are routed to the next lowest function companion controller, and so on. 第一个 port 对应低号的 companion Controller。
• 0x1：The port routing is explicitly enumerated by the first N_PORTS elements of the HCSP-PORTROUTE array.

Port Power Control，此位指示此 Host Controller 是否实现端口电源控制开关。

Number of physical downstream ports，表示此 Host Controller 具有多少个下行的物理端口。

When bit [7] is zero, the value of the least significant3 bits indicates the number of micro-frames a host controllercan hold a set of isochronous data structures (one or more)before flushing the state.When bit [7] is a one, then host software assumes the hostcontroller may cache an isochronous data structure for anentire frame.

• 0x0：the host controller doesn’t support the park featurefor high-speed queue heads in the Asynchronous Schedule.
• 0x1：the host controller supports the park feature forhigh-speed queue heads in the Asynchronous Schedule.

• 0x0：data structures using 32-bit address memory pointers
• 0x1：data structures using 64-bit address memory pointers

Any other value in this register yields undefined results.

不支持此功能

If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and isR/W. Otherwise the bit must be a zero and is RO. Softwareuses this bit to enable or disable Park mode.When this bit is one, Park mode is enabled.When this bit is a zero, Park mode is disabled.

不支持此功能

If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is RO. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior.

EHCI 控制器轻复位。

This control bit is not required. If implemented, it allows the driver to reset the EHCI controller without affecting the state of the ports or the relationship to the companion host controllers. For example, the PORSTC registers should not be reset to their default values and the CF bit setting should not go to zero (retaining port ownership relationships).A host software read of this bit as zero indicates the Light Host Controller Reset has completed and it is safe for host software to re-initialize the host controller. A host software read of this bit as a one indicates the Light Host Controller Reset has not yet completed. If not implemented a read of this field will always return a zero.

This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advance statusbit in the USBSTS register. If the Interrupt on Async Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to a zero after it has set the Interrupt on Async Advance status bit in the USBSTS register to a one. Software should not write a one to this bit when the asynchronousschedule is disabled. Doing so will yield undefined results.

此功能不支持

EHCI 控制复位，复位完成后会自动清 0.

This control bit is used by software to reset the host controller. The effects of this on Root Hub registers are similar to a Chip Hardware Reset. When software writes a one to this bit, the Host Controller reset sits internal pipelines, timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. PCI Configuration registers are not affected by this reset. All operational registers, including port registers and port state machines are set to their initial values. Port ownership reverts to the companion host controller(s), with the side effects. Software must reinitialize the host controller in order to return the host controller to an operational state. This bit is set to zero by the Host Controller when the reset process is complete. Software cannot terminate the reset process early bywriting a zero to this register. Software should not set this bit to a one when the HCH alted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior.

• 0x1：Run，EHCI 调度器工作
• 0x0：Stop，EHCI 调度器停止

When set to a 1, the Host Controller proceeds with execution ofthe schedule. The Host Controller continues execution as longas this bit is set to a 1.When this bit is set to 0, the Host Controller completes thecurrent and any actively pipelined transactions on the USBand then halts. The Host Controller must halt within 16micro-frames after software clears the Run bit. The HC H altedbit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state. Software must not write a one to this field unless the host controller is in the Halted state (i.e. HCH alted in the USBSTS register is a one). Doing so will yield undefined results.

The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled(1) or disabled (0).

The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1)or disabled (0).

此位用于检测异步调度是否为空。

异步调度器向前中断

System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source.

The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size(as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles. Similarly, if the size is 512,the Host Controller sets this bit to a one every time FRINDEX[12] toggles.

The Host Controller sets this bit to a one when any portfor which the Port Owner bit is set to zero (see Section2.3.9) has a change bit transition from a zero to a oneor a Force Port Resume bit transition from a zero to aone as a result of a J-K transition detected on a suspended port. This bit will also be set as a result of the Connect Status Change being set to a one after system software has relinquished ownership of a connected port by writing a oneto a port’s Port Owner bit. This bit is allowed to be maintained in the Auxiliary power well. Alternatively, it is also acceptable that on a D3 toD0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, over-current change, enable/disable change and connect status change).

The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow). If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set.

• 0x0：无中断
• 0x1：出现中断

The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes).

异步调度器向前中断使能

When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit.

EHCI 系统错误中断使能

When this bit is a one, and the Host System Error Status bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System Error bit.

帧链表溢出中断使能

When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit.

端口归属变化中断使能

When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit.

USB 错误中断使能

When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit.

USB 中断使能

When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit.

帧索引号

The value in this register increments at the end of each time frame (e.g. micro-frame). Bits [12:3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames)before moving to the next index. The following illustrates values of N based on the value of the Frame List

此域对应空间地址的 Bit[31:12]

This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. These bits correspond to memory address signals [31:12],respectively.

Must be written as 0s.

此域为下一个将要被执行的异步 QH 的地址。

This 32-bit register contains the address of the next asynchronous queue head to be executed. These bits correspond to memory address signals [31:5],respectively. This field may only reference a Queue Head(QH).

配置标志位

Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. This field is zero if Port Power is zero.

Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. This field is zero if Port Power is zero.

Writing this bit to a one enables the port to be sensitiveto device connects as wake-up events. This field is zero if Port Power is zero.

端口归属

This bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0b to 1b transition. This bit unconditionally goes to 1b whenever the Configured bit is zero. System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device). Software writes a one to this bit when the attached device is not a high-speed device. A one in this bit means that a companion host controller owns and controls the port.

When power is not available on a port (i.e. PP equals a 0), the port is non- functional and will not report attaches,detaches, etc. When an over-current condition is detected on a powered port and the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port).

When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision2.0 is started. Software writes a zero to this bit to terminate the bus reset sequence. Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes. Note: when software writes this bit to a one, it must also write a zero to the Port Enable bit. Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero. The bit status will not read as a zero until after the reset has completed. If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g. set the Port Enable bit to a one). A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero. For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2ms of software writing this bit to a zero. The HCHalted bit in the USBSTS register should be a zero before software attempts to use this bit. The host controller may hold Port Reset asserted to a one when the HCHalted bit is a one. This field is zero if Port Power is zero.

• 0x0：端口不处于 Suspend 状态
• 0x1：使能端口进入 Suspend 状态

When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.A write of zero to this bit is ignored by the host controller. The host controller will unconditionally set this bit to a zero when:• Software sets the Force Port Resume bit to a zero (from a one).• Software sets the Port Reset bit to a one (from a zero).If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This field is zero if Port Power is zero.

This functionality defined for manipulating this bit depends on the value of the Suspend bit. For example, if the port is not suspended (Suspend and Enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are undefined. Software sets this bit to a 1 to drive resume signaling. The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected,the Port Change Detect bit in the USBSTS register is also set to a one. If software sets this bit to a one, the host controller must not set the Port Change Detect bit. Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed‘K’) is driven on the port as long as this bit remains a one. Software must appropriately time the Resume and set this bitto a zero when the appropriate amount of time has elapsed. Writing a zero (from one) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle). This bit will remain a one until the port has switched to the high-speed idle. The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero. This field is zero if Port Power is zero.

Software clears this bit by writing a one to this bit position.

This bit will automatically transition from a one to a zero when the over current condition is removed.

For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point. Software clears this bit by writing a 1 to it. This field is zero if Port Power is zero.

Ports can only be enabled by the host controller as a partof the reset and enable. Software cannot enable a port bywriting a one to this field. The host controller will onlyset this bit to a one when the reset sequence determinesthat the attached device is a high-speed device.Ports can be disabled by either a fault condition (disconnectevent or other fault condition) or by host software. Notethat the bit status does not change until the port stateactually changes. There may be a delay in disabling or enablinga port due to other host controller and bus events.When the port is disabled (0b) downstream propagation ofdata is blocked on this port, except for reset.This field is zero if Port Power is zero.

Indicates a change has occurred in the port’s Current Connect Status. The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example,the insertion status changes twice before system software has cleared the changed condition, hub hardware will be “setting”an already-set bit (i.e., the bit will remain set). Softwa resets this bit to 0 by writing a 1 to it. This field is zero if Port Power is zero.

This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power is zero.

OHCI 版本

This read-only field contains the BCD representation ofthe version of the HCI specification that is implemented by this HC. For example, a value of 11h corresponds to version 1.1. All of the HC implementations that are compliant with this specification will have a value of 10h.

Remote Wakeup Enable

远程唤醒使能

This bit is used by HCD to enable or disable the remote wakeup feature upon the detection of upstream resume signaling. When this bit is set and the Resume Detected bit in Hc Interrupt Status is set, a remote wakeup is signaled to the host system. Setting this bit has no impact on the generation of hardware interrupt.

Remote Wakeup Connected

This bit indicates whether HC supports remote wakeup signaling. If remote wakeup is supported and used by the system it is the responsibility of system firmware to set this bit during POST. HC clears the bit upon a hardware reset but does not alter it upon a software reset. Remote wakeup signaling of the host system is host-bus-specific and is not described in this specification.

This bit determines the routing of interrupts generated by events registered in Hc Interrupt Status. If clear, all interrupts are routed to the normal host bus interrupt mechanism. If set,interrupts are routed to the System Management Interrupt. HCD clears this bit upon a hardware reset, but it does not alter this bit upon a software reset. HCD uses this bit as a tag to indicate the ownership of HC.

Host Controller Functional State for USB

A transition to USB OPERATIONAL from another state causes SOF generation to begin 1 ms later. HCD may determine whether HC has begun sending SOFs by reading the Start of Frame field of HcInterruptStatus. This field may be changed by HC only when in the USBSUSPEND state. HC may move from the USBSUSPEND state to the USBRESUME state after detecting the resume signaling from a downstream port. HC enters USBSUSPEND after a software reset, whereas it enters USBRESET after a hardware reset. The latter also resets theRoot Hub and asserts subsequent reset signaling to downstream ports.

Bulk List Enable，Bulk 链表使能

This bit is set to enable the processing of the Bulk list in the next Frame. If cleared by HCD, processing of the Bulk list does not occur after the next SOF. HC checks this bit whenever it determines to process the list. When disabled, HCD may modify the list. If HcBulkCurrentED is pointing to an ED to be removed, HCD must advance the pointer by updating HcBulkCurrentED before re-enabling processing of the list.

Control List Enable，控制链表使能

This bit is set to enable the processing of the Control list in the next Frame. If cleared by HCD, processing of the Control list does not occur after the next SOF. HC must check this bit whenever it determines to process the list. When disabled, HCD may modify the list. If HcControlCurrentED is pointing to an ED to be removed, HCD must advance the pointer by updating HcControlCurrentED before re-enabling processing of the list.

Isochronous Enable，同步端点描述符使能

This bit is used by HCD to enable/disable processing of isochronous EDs. While processing the periodic list in a Frame, HC checks the status of this bit when it finds an Isochronous ED (F=1). If set (enabled), HC continues processing the EDs. If cleared (disabled), HC halts processing of the periodic list (which now contains only isochronous EDs) and begins processing the Bulk/Control lists. Setting this bit is guaranteed to take effect in the next Frame (not the current Frame).

Periodic List Enable，周期链表使能

This bit is set to enable the processing of the periodic list in the next Frame. If cleared by HCD, processing of the periodic list does not occur after the next SOF. HC must check this bit before it starts processing the list.

Control Bulk Service Ratio，Control Bulk 服务比

SchedulingOverrunCount，调度器溢出计数

These bits are incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. This will be incremented when a scheduling overrun is detected even if Scheduling Overrun in HcInterruptStatus has already been set. This is used by HCD to monitor any persistent scheduling problems.

OwnershipChangeRequest，归属变化请求信号

This bit is set by an OS HCD to request a change of control of the HC. When set HC will set the Ownership Change field inHcInterruptStatus. After the changeover, this bit is cleared and remains so until the next request from OS HCD.

BulkListFilled，Bulk 链表填入 TD

This bit is used to indicate whether there are any TDs on the Bulk list. It is set by HCD whenever it adds a TD to an ED in the Bulk list. When HC begins to process the head of the Bulk list, it checksBF. As long as BulkListFilled is 0, HC will not start processing the Bulk list. If BulkListFilled is 1, HC will start processing the Bulk list and will set BF to 0. If HC finds a TD on the list,then HC will set BulkListFilled to 1 causing the Bulk listprocessing to continue. If no TD is found on the Bulk list, and if HCD does not set BulkListFilled, then BulkListFilled will still be 0 when HC completes processing the Bulk list and Bulk list processing will stop.

ControlListFilled，控制链表填入 TD

This bit is used to indicate whether there are any TDs on theControl list. It is set by HCD whenever it adds a TD to an EDin the Control list. When HC begins to process the head of the Control list, it checks CLF. As long as ControlListFilled is 0, HC will not start processing the Control list. If CF is 1, HC will start processing he Control list and will set ControlListFilled to 0. If HC finds a D on the list, then HC will set ControlListFilled to 1 causing the Control list processing to continue. If no TD is found on the Control list,and if the HCD does not set ControlListFilled, then ControlListFilled will still be 0 when HC completes processing the Control list and Control list processing will stop.

HostControllerReset，OHCI 软复位

This bit is set by HCD to initiate a software reset of HC. Regardless of the functional state of HC, it moves to the USBSUSPEND state in which most of the operational registers are reset except those stated otherwise; e.g., theInterruptRouting field of HcControl, and no Host bus accesses are allowed. This it is cleared by HC upon the completion of the reset operation. The reset operation must be completed within 10 ms. This bit, when set, should not cause a reset to the Root Hub and no subsequent reset signaling should be asserted to its downstream ports.

OwnershipChange，归属状态变化

This bit is set by HC when HCD sets the OwnershipChangeRequestfield in HcCommandStatus. This event, when unmasked, will always generate an System Management Interrupt (SMI) immediately. This bit is tied to 0b when the SMI pin is not implemented.

RootHubStatusChange

This bit is set when the content of HcRhStatus or thecontent of any of HcRhPortStatus[NumberofDownstreamPort]has changed.

FrameNumberOverflow

This bit is set when the MSb of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumberhas been updated.

UnrecoverableError

This bit is set when HC detects a system error not related to USB. HC should not proceed with any processing nor signaling before the system error has been corrected. HCD clears this bit after HC has been reset.

ResumeDetected

This bit is set when HC detects that a device on the USB is asserting resume signaling. It is the transition from no resume signaling to resume signaling causing this bit to beset. This bit is not set when HCD sets the USBRESUME state.

This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. HC also generates a SOF token at the same time.

This bit is set immediately after HC has written HcDoneHeadto HccaDoneHead. Further updates of the HccaDoneHead will not occur until this bit has been cleared. HCD should only clear this bit after it has saved the content of HccaDoneHead.

SchedulingOverrun

This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber. A scheduling overrun will also cause the SchedulingOverrunCountof HcCommandStatus to be incremented.

This is used by HCD as a Master Interrupt Enable.

• 0x0：Ignore
• 0x1：Enable interrupt generation due to Ownership Change.

• 0x0：Ignore
• 0x1：Enable interrupt generation due to Root Hub Status Change.

• 0x0：Ignore
• 0x1：Enable interrupt generation due to Frame Number Overflow.

• 0x0：Ignore
• 0x1：Enable interrupt generation due to Unrecoverable Error.

• 0x0：Ignore
• 0x1：Enable interrupt generation due to Resume Detect.

• 0x0：Ignore
• 0x1：Enable interrupt generation due to Start of Frame.

• 0x0：Ignore
• 0x1：Enable interrupt generation due to HcDoneHead Writeback.

• 0x0：Ignore
• 0x1：Enable interrupt generation due to Scheduling Overrun.

This field is set after a hardware or software reset.

• 0x0：Ignore
• 0x1：Disable interrupt generation due to Ownership Change.

• 0x0：Ignore
• 0x1：Disable interrupt generation due to Root Hub Status Change.

• 0x0：Ignore
• 0x1：Disable interrupt generation due to Frame Number Overflow.

• 0x0：Ignore
• 0x1：Disable interrupt generation due to Unrecoverable Error.

• 0x0：Ignore
• 0x1：Disable interrupt generation due to Resume Detect.

• 0x0：Ignore
• 0x1：Disable interrupt generation due to Start of Frame.

• 0x0：Ignore
• 0x1：Disable interrupt generation due to HcDoneHead Writeback.

• 0x0：Ignore
• 0x1：Disable interrupt generation due to Scheduling Overrun.

This is the base address of the Host Controller Communication Area.

The alignment is evaluated by examining the number of zeroes in the lower order bits. The minimum alignment is 256 bytes;therefore, bits 0 through 7 must always return ‘0’ when read.

PeriodCurrentED

This is used by HC to point to the head of one of thePeriodic lists which will be processed in the current Frame.The content of this register is updated by HC after aperiodic ED has been processed. HCD may read the contentin determining which ED is currently being processed atthe time of reading.

Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary. So the lower bits in the PCED, through bit 0 to bit 3 must be zero in this field.

ControlHeadEDHC traverses the Control list starting with the HcControlHeadEDpointer. The content is loaded from HCCA during theinitialization of HC.

Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary. So the lower bits in the CHED, through bit 0 to bit 3 must be zero in this field.

ControlCurrentEDThis pointer is advanced to the next ED after serving thepresent one. HC will continue processing the list from where it left off in the last Frame. When it reaches the end of the Control list, HC checks the ControlListFilled of inHcCommandStatus. If set, it copies the content ofHcControlHeadED to HcControlCurrentED and clears the bit. If not set, it does nothing. HCD is allowed to modify this register only when the ControlListEnable of HcControl iscleared. When set, HCD only reads the instantaneous valueof this register. Initially, this is set to zero to indicate the end of the Control list.

Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary. So the lower bits in the CCED, through bit 0 to bit 3 must be zero in this field.

BulkHeadED

HC traverses the Bulk list starting with the HcBulkHeadEDpointer. The content is loaded from HCCA during the initialization of HC.

Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary. So the lower bits in the BHED, through bit 0 to bit 3 must be zero in this field.

BulkCurrentED

This is advanced to the next ED after the HC has served the present one. HC continues processing the list from where it left off in the last Frame. When it reaches the end of the Bulk list, HC checks the ControlListFilled of HcControl. If set, it copies the content of HcBulkHeadED to HcBulkCurrentED and clears the bit. If it is not set, it does nothing. HCD is only allowed to modify this register when the BulkListEnable of HcControl is cleared. When set, the HCD only reads the instantaneous value of this register. This is initially set to zero to indicate the end of the Bulk list.

Because the general TD length is 16 bytes, the memory structure for the TD must be aligned to a 16-byte boundary. So the lower bits in the BCED, through bit 0 to bit 3 must be zero in this field.

DoneHead

When a TD is completed, HC writes the content of HcDoneHeadto the NextTD field of the TD. HC then overwrites the content of HcDoneHead with the address of this TD. This is set to zero whenever HC writes the content of this register to HCCA. It also sets the WritebackDoneHead of HcInterruptStatus.

FrameIntervalToggle

HCD toggles this bit whenever it loads a new value toFrameInterval.

FSLargestDataPacket

This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. The counter value represents the largest amount of data in bits which can be sent or received by the HC in a single transaction at any given time without causing scheduling overrun. The field value is calculated by the HCD.

FrameInterval

This specifies the interval between two consecutive SOFs in bit times. The nominal value is set to be 11,999. HCD should store the current value of this field before resetting HC. By setting the HostControllerReset field of HcCommandStatus as this will cause the HC to reset this field to its nominal value. HCD may choose to restore the stored value upon the completion of the Reset sequence.

FrameRemainingToggle

This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever Frame Remaining reaches 0. This bit is used by HCD for the synchronization between Frame Interval and Frame Remaining.

FrameRemaining

This counter is decremented at each bit time. When it reaches zero, it is reset by loading the Frame Interval value specified in HcFmInterval at the next bit time boundary. When entering the USBOPERATIONAL state, HC re-loads the content with the Frame Interval of HcFmInterval and uses the updated value from the next SOF.

FrameNumber

This is incremented when HcFmRemaining is re-loaded. It will be rolled over to 0h after ffffh. When entering the USBOPERATIONAL state, this will be incremented automatically. The content will be written to HCCA after HC has incremented the FrameNumber at each frame boundary and sent a SOF but before HC reads the first ED in that Frame. After writing to HCCA, HC will set the StartofFrame in HcInterruptStatus.

After a hardware reset, this field is cleared. This is then set by HCD during the HC initialization. The value is calculated roughly as 10% off from HcFmInterval. A typical value will be 3E67h. When HcFmRemaining reaches the value specified, processing of the periodic lists will have priority over Control/Bulk processing. HC will therefore start processing the Interrupt list after completing the current Control or Bulk transaction that is in progress.

LSThreshold

This field contains a value which is compared to the Frame Remaining field prior to initiating a Low Speed transaction. The transaction is started only if Frame Remaining this field. The value is calculated by HCD with the consideration of transmission and setup overhead.

PowerOnToPowerGoodTime

POWER 启动时间

This byte specifies the duration HCD has to wait before accessing a powered-on port of the Root Hub. It is implementation-specific. The unit of time is 2 ms. The duration is calculated as POTPGT * 2 ms.

NoOverCurrentProtection

不支持过流保护

OverCurrentProtectionMode

过流保护模式

DeviceType

This bit specifies that the Root Hub is not a compound device. The Root Hub is not permitted to be a compound device. This field should always read/write 0.

NoPowerSwitching

不支持电源开关

PowerSwitchingMode 电源开关模式

NumberDownstreamPorts

下行端口的数目

These bits specify the number of downstream ports supported by the Root Hub. It is implementation-specific. The minimum number of ports is 1. The maximum number of ports supported by OpenHCIis 15.

PortPowerControlMask 端口电源控制屏蔽

DeviceRemovableDevice 可移除设置

ClearRemoteWakeupEnable 清除远程唤醒使能

Writing a ‘1’ clears DeviceRemoveWakeupEnable.

Writing a ‘0’ has no effect.

This bit is set by hardware when a change has occurred to the OCI field of this register. The HCD clears this bit by writing a ‘1’. Writing a ‘0’ has no effect.

In global power mode (PowerSwitchingMode=0), This bit is written to ‘1’ to turn on power to all ports (clear PortPowerStatus). In per-port power mode, it sets PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing a ‘0’ has no effect.

DeviceRemoteWakeupEnable

(write)SetRemoteWakeupEnable.

Writing a ‘1’ sets DeviceRemoveWakeupEnable. Writing a ‘0’ hasno effect.

OverCurrentIndicator

This bit reports over current conditions when the global reporting is implemented. When set, an over current condition exists. When cleared, all power operations are normal. If per-port over current protection is implemented this bit is always ‘0’.

In global power mode (PowerSwitchingMode=0), This bit is written to ‘1’ to turn off power to all ports (clear PortPowerStatus).In per-port power mode, it clears PortPowerStatus only on portswhose PortPowerControlMask bit is not set. Writing a ‘0’ has noeffect.

PortResetStatusChange

端口 RESET 状态改变

PortOverCurrentIndicatorChange

PortSuspendStatusChange

This bit is set when the full resume sequence has been completed. This sequence includes the 20-s resume pulse, LSEOP, and 3-ms resychronization delay. The HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect. This bit is also cleared when ResetStatusChange is set.0x0：resume is not completed0x1：resume completed

PortEnableStatusChange

ConnectStatusChange

This bit is set whenever a connect or disconnect event occurs. The HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.

Note: If the DeviceRemovable[NDP] bit is set, this bit is setonly after a Root Hub reset to inform the system that the device is attached.

(read) LowSpeedDeviceAttached

(write) ClearPortPower

The HCD clears the PortPowerStatus bit by writing a ‘1’ to thisbit. Writing a ‘0’ has no effect.

(read) PortPowerStatus

(write) SetPortPower

The HCD writes a ‘1’ to set the PortPowerStatus bit. Writing a‘0’ has no effect.

Note: This bit is always reads ‘1b' if power switching is not supported.

(read) PortResetStatus

(write) SetPortReset

The HCD sets the port reset signaling by writing a ‘1’ to this bit. Writing a ‘0’ has no effect. If CurrentConnectStatus is cleared, this write does not set PortResetStatus, but insteadsets ConnectStatusChange. This informs the driver that it attempted to reset a disconnected port.

(read) PortOverCurrentIndicator

(write) ClearSuspendStatus

The HCD writes a ‘1’ to initiate a resume. Writing a ‘0’ has noeffect. A resume is initiated only if PortSuspendStatus is set.

(read) PortSuspendStatus

(write) SetPortSuspend

The HCD sets the PortSuspendStatus bit by writing a ‘1’ to this bit. Writing a ‘0’ has no effect. If CurrentConnectStatus is cleared,this write does not set PortSuspendStatus; instead it sets Connect-StatusChange. This informs the driver that it attempted to suspend a disconnected port.

(read) PortEnableStatus

This bit indicates whether the port is enabled or disabled. The Root Hub may clear this bit when an over current condition,disconnect event, switched-off power, or operational bus error such as babble is detected. This change also causes PortEnabled-StatusChange to be set. HCD sets this bit by writing SetPortEnableand clears it by writing ClearPortEnable.

This bit cannot be set when CurrentConnectStatus is cleared.

(write) SetPortEnable

The HCD sets PortEnableStatus by writing a ‘1’. Writing a ‘0’ has no effect. If CurrentConnectStatus is cleared, this write does notset PortEnableStatus, but instead sets ConnectStatusChange. This informs the driver that it attempted to enable a disconnected port.

(read) CurrentConnectStatus

(write) ClearPortEnable

The HCD writes a ‘1’ to this bit to clear the PortEnableStatus bit. Writing a ‘0’ has no effect. The CurrentConnectStatus is not affected by any write.

Note: This bit is always read ‘1b' when the attached device isnonremovable (DeviceRemoveable[NDP]).

This signal is used only for simulation.

Port Overcurrent Indication From Application

When asserted by the application, the corresponding port enters Disable state. This signal controls both EHCI and OHCI controller port state machines. Depending on ownership of the port, the corresponding EHCI or OHCI controller generates an Overcurrent Detect interrupt.

This is an asynchronous primary input to the host core. When the OHCI clocks are suspended, the system has to assert this signal to start the clocks (12 and 48 MHz). This should be deasserted after the clocks are started and before the host is suspended again. (Host is suspended means HCFS =SUSPEND or all the OHCI ports are suspended).

0x0：No effect

0x1：This strap signal enables automatic port power disable in the host controller.

When this signal is active, if an over-current condition is detected on a powered port and PPC is 1, the PP bit in each affected port is automatically transitioned by the host controller from a 1 to 0, removing power from the port.

• 0x0：No effect
• 0x1：This strap signal enables the function to automaticallyset/clear the PHY’s port power setting to reflect the Host’sport power setting

• 0x0: 8bit
• 0x1: 16bit

• 0x0：ULPI enable
• 0x1：ULPI Disable，use UTMI

Common Block Power-Down Control

0x0：In Suspend or Sleep mode, the XO, Bias, and PLL blocksremain powered. 0x1：In Suspend mode, the XO, Bias, and PLL blocks are powereddown. In Sleep mode, the Bias and PLL blocks are powereddown.

Analog Test Pin Select0x0：Analog test voltages cannot be viewed or applied on either ANALOGTEST or ID0. 0x1：Analog test voltages can be viewed or applied on ID0. 0x2：Analog test voltages can be viewed or applied on ANALOGTEST. 0x3：Reserved. Invalid setting.

Test Data Write Bus

Disconnect Threshold Adjustment

Squelch Threshold Adjustment

VBUS Valid Threshold Adjustment

Transmitter High-Speed Crossover Adjustment

HS Transmitter Rise/Fall Time Adjustment

USB Source Impedance Adjustment

In some applications, there can be significant series resistance on the D+ and D– paths between the transceiver and cable. This bus adjusts the driver source impedance to compensate for added series resistance on the USB.

Note: Any setting other than the default can result in source impedance variation across process, voltage, and temperature conditions that does not meet USB 2.0 specification limits.0x0：Source impedance is increased by approximately 1.5 Ω.0x1：Design default0x2：Source impedance is decreased by approximately 2 Ω.0x3：Source impedance is decreased by approximately 4 Ω.

HS Transmitter Pre-Emphasis Current ControlThis signal controls the amount of current sourced to DP0 and DM0after a J-to-K or K-to-J transition. The HS Transmitter pre-emphasis current is defined in terms of unit amounts.One unit amount is approximately 600 μA and is defined as 1Xpre-emphasis current.0x0 (design default): HS Transmitter pre-emphasis is disabled.0x1: HS Transmitter pre-emphasis circuit sources 1X pre-emphasis current.0x2: HS Transmitter pre-emphasis circuit sources 2X pre-emphasis current.0x3: HS Transmitter pre-emphasis circuit sources 3X pre-emphasis current.

Test Data Read Bus