功能描述
PLL
模拟电路 PLL 用于产生时钟供给整个芯片。
CMU PLL 用途及特性列出了各个 PLL 的用途及特性。
名称 | 用途 | 典型频率 | 展频 |
---|---|---|---|
PLL_INT0 | CPU | 480 MHz | 不支持 |
PLL_INT1 | AXI/ AHB/ APB/CE/DE/GE/VE/DVP/PWMCS/TA_IF/EDT_IF/BISS_IF/SDFM/UART/PWMI2S/AUDIO | 1.2 GHz | 不支持 |
PLL_FRA0 | XSPI/ SPI/ SDMC | 800 MHz | 展频 |
PLL_FRA2 | LCD/ LVDS/ MIPI_DSI | - | 展频 |
CLKOUT
时钟输出用于输出时钟给芯片外设使用, 总共四路 CLKOUT,可选来源为 ,可配置 1~256 除频, CLKOUT 通路如下图所示。
模块时钟
模块名称 | 总线时钟 | 模块时钟源 | 模块时钟极限频率 | 备注 |
---|---|---|---|---|
E907 CORE | - | PLL_INT0 | 480 MHz | - |
E907 PLIC | - | PLL_INT0÷2 | 240 MHz | - |
E907 CLINT | - | PLL_INT0÷2 | 240 MHz | - |
E907 DM | - | CLK_24M | 24 MHz | - |
AXI | AXI | - | 200 MHz | - |
AHB | AHB | - | 200 MHz | - |
APB0 | APB0 | - | 100 MHz | - |
APB1 | APB1 | - | 24 MHz | - |
BROM | AXI | - | - | - |
SRAM | AXI | - | - | - |
AHB Matrix | AHB | - | - | - |
DMA | AHB | - | - | - |
CE | AHB | PLL_INT1 | 200 MHz | - |
USB DEV | AHB | - | - | - |
USB PHY | - | CLK_24M | - | - |
EMAC | AHB | PLL_INT1 | 50 MHz | - |
XSPI | AHB | PLL_FRA0 | 400 MHz | - |
SPI0 | AHB | PLL_FRA0 | 100 MHz | - |
SPI1 | AHB | PLL_FRA0 | 100 MHz | - |
SPI2 | AHB | PLL_FRA0 | 100 MHz | - |
SPI3 | AHB | PLL_FRA0 | 100 MHz | - |
CORDIC | AHB | - | - | - |
HCL | AHB | - | - | - |
PBUS | AHB | - | - | - |
SYSCFG | APB0 | CLK_24M | 24 MHz | - |
CMU | APB0 | - | - | - |
SPI_ENC | APB0 | HCLK | - | - |
PWMCS | APB0 | PLL_INT1 | 200 MHz | - |
ADC | APB0 | PLL_INT1 | 100 MHz | - |
AXICFG | APB0 | - | - | - |
GPIO | APB0 | - | - | - |
UART0 | APB0 | PLL_INT1 | 60 MHz | - |
UART1 | APB0 | PLL_INT1 | 60 MHz | - |
UART2 | APB0 | PLL_INT1 | 60 MHz | - |
UART3 | APB0 | PLL_INT1 | 60 MHz | - |
UART4 | APB0 | PLL_INT1 | 60 MHz | - |
UART5 | APB0 | PLL_INT1 | 60 MHz | - |
UART6 | APB0 | PLL_INT1 | 60 MHz | - |
UART7 | APB0 | PLL_INT1 | 60 MHz | - |
TA-IF | APB0 | PLL_INT1 | 240 MHz | - |
EDT-IF | APB0 | PLL_INT1 | 240 MHz | - |
BISS-IF | APB0 | PLL_INT1 | 240 MHz | - |
SDFM | APB0 | PLL_INT1 | 240 MHz | - |
WDOG | APB1 | CLK_32K | 32 KHz | - |
WRI | APB1 | CLK_24M | 24 MHz | - |
SID | APB1 | CLK_24M | 24 MHz | - |
GTC | APB1 | - | - | - |
I2C0 | APB1 | - | - | - |
I2C1 | APB1 | - | - | - |
I2C2 | APB1 | - | - | - |
I2C3 | APB1 | - | - | - |
CAN0 | APB1 | - | - | - |
CAN1 | APB1 | - | - | - |
PWM | APB1 | PLL_INT1 | 100 MHz | - |
ADCIM | APB1 | PLL_INT1 | 100 MHz | - |
THS | APB1 | - | - | - |
CPM | APB1 | - | - | - |
模块开关时序
USB
- 打开时序:
ctrlclk1->phyclk1->100us->phyrst1->ctrlrst1
- 关闭时序:
ctrlrst0->phyrst0->phyclk0->ctrlclk0
其他模块c
- 打开时序:
modclk1->busclk1->rst1
- 关闭时序:
rst0->busclk0->modclk0